april 2013 ?2000 fairchild semiconductor corporation FQD7N10L rev. c0 www.fairchildsemi.com 1 FQD7N10L n-channel qfet ? mosfet FQD7N10L n-channel qfet ? mosfet 100 v, 5.8 a, 350 m? description this n-channel enhancement mode power mosfet is produced using fairchild semiconductor ? ?s proprietary planar stripe and dmos technology. this advanced mosfet technology has been es pecially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength. these devices are suitable for switched mode power supplies, audio amplifier, dc motor control, and variable switching power applications. features ? 5.8 a, 100 v, r ds(on) = 350 m? (max.) @ v gs = 10 v, id = 2.9 a ? low gate charge (typ. 4.6 nc) ? low crss (typ. 12 pf) ? 100% avalanche tested absolute maximum ratings t c = 25c unless otherwise noted thermal characteristics symbol parameter FQD7N10L unit v dss drain-source voltage 100 v i d drain current - continuous (t c = 25c) 5.8 a - continuous (t c = 100c) 3.67 a i dm drain current - pulsed (note 1) 23.2 a v gss gate-source voltage ? 20 v e as single pulsed avalanche energy (note 2) 50 mj i ar avalanche current (note 1) 5.8 a e ar repetitive avalanche energy (note 1) 2.5 mj dv/dt peak diode recovery dv/dt (note 3) 6.0 v/ns p d power dissipation (t a = 25c) * 2.5 w power dissipation (t c = 25c) 25 w - derate above 25c 0.2 w/c t j , t stg operating and storage temperature range -55 to +150 c t l maximum lead temperature for soldering purposes, 1/8 " from case for 5 seconds 300 c symbol parameter FQD7N10L unit r ? jc thermal resistance, junction-to-case, max. 5.0 c /w r ? ja thermal resistance, junction-to-ambient * 50 c /w r ? ja thermal resistance, junction-to-ambient, max. 110 c /w * when mounted on the minimum pad size recommended (pcb mount) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? s d g s d g d-pak
?2000 fairchild semiconductor corporation FQD7N10L rev. c0 www.fairchildsemi.com 2 FQD7N10L n-channel qfet ? mosfet electrical characteristics t c = 25c unless otherwise noted notes: 1. repetitive rating : pulse width li mited by maximum junction temperature 2. l = 2.23mh, i as = 5.8a, v dd = 25v, r g = 25 : starting t j = 25c 3. i sd 7.3a, di/dt 300a/ p s, v dd bv dss, starting t j = 25c 4. essentially independent of operating temperature symbol parameter test conditions min typ max unit off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 p a 100 -- -- v ' bv dss / ' t j breakdown voltage temperature coefficient i d = 250 p a, referenced to 25c -- 0.1 -- v/c i dss zero gate voltage drain current v ds = 100 v, v gs = 0 v -- -- 1 p a v ds = 80 v, t c = 125c -- -- 10 p a i gssf gate-body leakage current, forward v gs = 20 v, v ds = 0 v -- -- 100 na i gssr gate-body leakage current, reverse v gs = -20 v, v ds = 0 v -- -- -100 na on characteristics v gs(th) gate threshold voltage v ds = v gs , i d = 250 p a 1.0 -- 2.0 v r ds(on) static drain-source on-resistance v gs = 10 v, i d = 2.9 a v gs = 5 v, i d = 2.9 a -- 0.275 0.300 0.35 0.38 : g fs forward transconductance v ds = 30 v, i d = 2.9 a -- 4.6 -- s dynamic characteristics c iss input capacitance v ds = 25 v, v gs = 0 v, f = 1.0 mhz -- 220 290 pf c oss output capacitance -- 55 72 pf c rss reverse transfer capacitance -- 12 15 pf switching characteristics t d(on) turn-on delay time v dd = 50 v, i d = 7.3 a, r g = 25 : (note 4) -- 9 30 ns t r turn-on rise time -- 100 210 ns t d(off) turn-off delay time -- 17 45 ns t f turn-off fall time -- 50 110 ns q g total gate charge v ds = 80 v, i d = 7.3 a, v gs = 5 v (note 4) -- 4.6 6.0 nc q gs gate-source charge -- 1.0 -- nc q gd gate-drain charge -- 2.6 -- nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current -- -- 5.8 a i sm maximum pulsed drain-source diode forward current -- -- 23.2 a v sd drain-source diode forward voltage v gs = 0 v, i s = 5.8 a -- -- 1.5 v t rr reverse recovery time v gs = 0 v, i s = 7.3 a, di f / dt = 100 a/ p s -- 70 -- ns q rr reverse recovery charge -- 140 -- nc
?2000 fairchild semiconductor corporation FQD7N10L rev. c0 www.fairchildsemi.com 3 FQD7N10L n-channel qfet ? mosfet 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 10 -1 10 0 10 1 25 ?
FQD7N10L n-channel qfet ? mosfet ?2000 fairchild semiconductor corporation FQD7N10L rev. c0 www.fairchildsemi.com 4 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -1 10 0 figure 9. maximum safe operating area figure 10. maximum drain current vs. case temperature figure 7. breakdown voltage variation vs. temperature figure 8. on-resistance variation vs. temperature figure 11. transient thermal response curve t 1 p dm t 2
?2000 fairchild semiconductor corporation FQD7N10L rev. c0 www.fairchildsemi.com 5 FQD7N10L n-channel qfet ? mosfet charge v gs 5v q g q gs q gd 3ma v gs dut v ds 300nf 50k
FQD7N10L n-channel qfet ? mosfet ?2000 fairchild semiconductor corporation FQD7N10L rev. c0 www.fairchildsemi.com 6 peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period --------------------------
?2000 fairchild semiconductor corporation FQD7N10L rev. c0 www.fairchildsemi.com 7 FQD7N10L n-channel qfet ? mosfet package dimensions dpak
?2000 fairchild semiconductor corporation FQD7N10L rev. c0 www.fairchildsemi.com 8 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairch ild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions , specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a sign ificant injury of the user. 2. a critical component in any com ponent of a life support, device, or system whose failure to perform can be reasonably ex pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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FQD7N10L n-channel qfet ? mosfet
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